Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as ASIC devices (Application Specific Integrated Circuits). PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology.
Regardless of the type of PLD targeted by a customer design, it is necessary for the PLD user to provide a description of the circuit to be implemented. The user circuit description can be provided, for example, in the form of an HDL (high-level design language) description of the logical functionality of the circuit, a netlist (a listing of low-level circuit elements or gates in the circuit and the interconnections between them), or in some other format such as a configuration data file indicating the exact implementation of the design in the target PLD.
To reduce the time required to implement a user circuit in a PLD, PLD manufacturers often provide pre-designed circuits (“modules,” also called cores or macros) that can be included in a customer's design. A module can be included in a design, for example, by including a symbol for the module in a schematic, or by directly instantiating the module in an HDL description or in a netlist.
The design description, which may or may not include module instantiations, is provided by the user to PLD implementation software, which converts the design description to a configuration data file for the targeted PLD. The configuration data file is then used to program the PLD using an appropriate method such as those described above.
System designs often include, in addition to a user circuit, basic control devices such as push-buttons, manual switches, DIP switches, and so forth, which are used to provide input signals to the user circuit. The systems also often include status indicators such as discrete LEDs (light-emitting diodes), 7-segment LED displays, liquid crystal displays, and so forth, which are used to display output data from the user circuit.
FIG. 1 shows a typical system design. The system of FIG. 1 includes a PLD 100 in which a user circuit 101 has been implemented, external control input devices 102, and external status output devices 103. A first communication link 104 provides a communication channel through which external control input devices 102 provide input data to user circuit 101. A second communication link 105 provides a communication channel through which external status output devices 103 receive output data from user circuit 101.
PLD 100, input devices 102, and output devices 103 are separately mounted on a printed circuit (PC) board. Communication links 104, 105 are implemented using traces manufactured as part of the customized PC board. The communication links are coupled to user circuit 101 through device pins (e.g., IOBs) of the PLD and package pins of the PLD package.
The system of FIG. 1 has its limitations. To provide control input data to the user circuit, or to receive status output data from the user circuit, the user must be in the physical presence of the PC board. Communication links 104, 105 pass through device pins (e.g., IOBs) of the PLD and package pins of the PLD package, which often uses device or package pins that are needed for other purposes. The use of external control and status devices consumes significant area on the PC board, both for the devices themselves and for the traces between the PLD and the devices. Thus, the addition of control and status devices increases the cost of the system. The external devices also consume additional power, which is often a factor in system design. Finally, it is not uncommon for a system to require additional control and/or status devices after the system design was presumed complete. Such an alteration requires a modification of the PC board.
These limitations are partially addressed by the provision of Integrated Logic Analyzer cores (ILA modules). ILA modules are implemented in the PLD along with a user circuit. The ILA modules monitor various output signals from the user circuit, analyze the data from the output signals, and provide data pertaining to the output signal values to a host computer system. For example, Xilinx, Inc. provides a ChipScope™ software product that includes a collection of ILA modules. Version 4.1i of the ChipScope software and the accompanying ILA modules are described in detail in the “ChipScope™ Software and ILA Cores User Manual”, published Oct. 19, 2001 and available from Xilinx, Inc., which is hereby incorporated herein by reference.
FIG. 2 shows a system that includes a PLD with an ILA module. The system includes a PLD 200, a host computer 210, and a communication link 220 between PLD 200 and host computer 210. Loaded on host computer 210 is ILA software (e.g., the ChipScope software) that can be used to retrieve status output data from the PLD via the communication link. PLD 200 includes three logic blocks implemented using the programmable resources of the PLD. The three logic blocks include user circuit 201, embedded ILA module 202, and embedded communication module 203.
User circuit 201 is a circuit provided by the user, the circuit that the user wishes to monitor. ILA module 202 is a logic block typically provided by the FPGA manufacturer, that provides logic analyzer functions of signals provided by user circuit 201.
Communication module 203 is also typically provided by the FPGA manufacturer, and includes logic that links the ILA module 202 with communications link 220 to the host computer 210. For example, communication module 203 can implement a link between the ILA module and JTAG circuitry already present in the PLD. Communication link 220 also typically includes a direct connection to user circuit 201, i.e., a connection that bypasses communication module 203 and ILA module 202. This connection is shown as a dotted line in FIG. 2.
The system of FIG. 2 provides the ability to monitor output signals from user circuit 201. However, the system of FIG. 2 does not provide the ability to control input signals to the user circuit, e.g., emulating the functions of device 102 of FIG. 1. Therefore, it is desirable to provide systems and methods providing the control functionality of the system of FIG. 1 while addressing one or more of the limitations described above in connection with that figure.